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PIC18F87J11 FAMILY
DS39778E-page 58
2007-2012 Microchip Technology Inc.
A CM Reset behaves similarly to a Master Clear Reset,
RESET
instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
5.6
Power-up Timer (PWRT)
PIC18F87J11 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J11 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32
s = 66 ms. While the PWRT
is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC Parameter 33 for details.
5.6.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
Figure 5-5
and
Figure 5-6
all
depict
time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse and if
MCLR is kept low long enough, the PWRT will expire.
Bringing MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 5-1:
TIME-OUT IN VARIOUS SITUATIONS
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
Oscillator
Configuration
Power-up(2) and Brown-out Reset
Exit from
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
HS, XT, LP
66 ms(1) + 1024 TOSC
1024 TOSC
EC, ECIO
66 ms(1)
——
RC, RCIO
66 ms(1)
——
INTIO1, INTIO2
66 ms(1)
——
Note 1:
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2:
2 ms is the nominal time required for the PLL to lock.
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
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